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? semiconductor components industries, llc, 2012 march, 2012 ? rev. 0 1 publication order number: NCL30002/d NCL30002 power factor corrected buck led driver the NCL30002 is a switch mode power supply controller intended for low to medium power single stage power factor (pf) corrected led drivers. the device operates as a critical conduction mode (crm) buck controller to regulate led current at a high power factor for a specific line voltage range. the current limit threshold is tightly trimmed allowing open loop control techniques to reduce parts count while maintaining accurate current regulation and high power factor. crm operation is particularly suited for led applications as very high efficiency can be achieved even at low power levels. these are important in led lighting to comply with regulatory requirements and meet overall system luminous efficacy requirements. in crm, the switching frequency will vary with line and load. switching losses are low as recovery losses in the output rectifier are negligible since the current goes to zero prior to reactivating the main mosfet switch. the device features a programmable on time limiter, zero current detect sense block, gate driver, trans ? conductance error amplifier as well as all pwm control circuitry and protection functions required to implement a crm switch mode power supply. moreover, for high efficiency, the device features low startup current enabling fast, low loss charging of the v cc capacitor. the current sense protection threshold has been set at 485 mv to minimize power dissipation in the external sense resistor. to support the environmental operation range of solid state lighting, the device is specified across a wide junction temperature range of ? 40 c to 125 c. features ? very low 24 a typical startup current ? cycle ? by ? cycle current protection ? tightly trimmed low current sense threshold of 485 mv 2% ? low 2 ma typical operating current ? source 500 ma / sink 800 ma totem pole gate driver ? wide operating temperature range ? enable function and overvoltage protection ? these devices are pb ? free, halogen free/bfr free and are rohs compliant typical applications ? led driver power supplies ? led based bulbs ? commercial and residential led fixtures http://onsemi.com soic ? 8 d suffix case 751 marking diagram pin connection 1 8 a = assembly location l = wafer lot y = year w = work week = pb ? free package l0002 alyw 1 8 mfp comp ct cs v cc drv gnd zcd (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. NCL30002dr2g soic ? 8 (pb ? free) 2500 / tape & reel
NCL30002 http://onsemi.com 2 + figure 1. block diagram e/a demag uvp fault leb 195 ns* off timer reset pwm r q s (enable ea) drv q all sr latches are reset dominant zcd clamp ovp v cc drv gnd v dd v cc mfp zcd c t cs comp + + ? v ovp ? + v uvp r mfp v ref + g m ? + v control r q s q r q s q r q s q v zcd(trig) ? + + v zcd(arm) + + ? + ? + v dd add ct offset 270 a* v eah clamp ? + 180 s* v cc management v dd power good v dd ocp v ilim * typical values shown
NCL30002 http://onsemi.com 3 table 1. pin function description pin name function 1 mfp the multi ? function pin is connected to the internal error amplifier. by pulling this pin below the v uvp threshold, the controller is disabled. in addition, this pin also has an over voltage comparator which will disable the controller in the event of a fault. 2 comp the comp pin is the output of the internal error amplifier. a compensation network connected between this pin and ground sets the loop bandwidth. 3 c t the c t pin sources a regulated current to charge an external timing capacitor. the pwm circuit controls the power switch on time by comparing the c t voltage to an internal voltage derived from v control . the c t pin discharges the external timing capacitor at the end of the on time cycle. 4 cs the cs input threshold is precisely trimmed to accurately sense the instantaneous switch current in the external mosfet. this signal is conditioned by an internal leading edge blanking circuit. the current limit threshold is tightly trimmed for precise peak current control. 5 zcd the voltage of an auxiliary zero current detection winding is sensed at this pin. when the zcd control block circuit detects that the winding current has gone to zero, a control signal is sent to the gate drive block to turn on the external mosfet. 6 gnd this is the analog ground for the device. all bypassing components should be connected to the gnd pin with a short trace length. 7 drv the high current capability of the totem pole gate drive (+0.5/ ? 0.8 a) makes it suitable to effectively drive high gate charge power mosfets. the driver stage provides both passive and active pull down circuits that force the output to a voltage less than the turn ? on threshold voltage of the power mosfet when v cc(on) is not reached. 8 v cc this pin is the positive supply of the controller. the circuit starts to operate when v cc exceeds v cc(on) , nominally 12 v and turns off when v cc goes below v cc(off) , typically 9.5 v. after startup, the operating range is 10.2 v up to 20 v.
NCL30002 http://onsemi.com 4 figure 2. simplified pfc buck application dovp lemi1 d4 + ? ac1 ac2 rstart r15 f1 lemi2 l4 u1 NCL30002 r8 ct rin qbuck rfb rsense c4 rtop rv1 mov rbottom ccomp lout cout cvcc c6 rzcd dbuck dvcc rgdrv led + led ? ac1 ac2 cs 4 vcc 8 zcd 5 gnd 6 ct 3 mfp 1 comp 2 drv 7 r2 (optional) hvdc filter caps current sense start ? up resistors output filter cap ovp zener zcd feed forward compensation vcc bootstrap on time capacitor emi filter/ rectifier / surge suppression cfilter overview figure 2 illustrates the basic NCL30002 architecture for a non-isolated low power high power factor led driver. one of the notable features of this architecture is the open loop control. notice that there is no direct measurement of the led current. tight peak current control coupled with line feed-forward compensation to vary the on-time allows for accurate led drive current. fortunately in the vast majority of led bulb and luminaire applications, the led forward voltage range is well bounded and the line voltage may be limited to one operating range. this is a huge advantage which makes the simplicity of open loop control possible. buck switching on the low side eliminates a floating gate drive but references the led to the hv rail. buck converters only produce output when the input voltage exceeds the load voltage. consequently, the input current goes to zero near the zero crossing of the line. the exact phase angle of this event depends on the led string voltage and the line voltage. unlike the boost pfc, the buck pfc has increased distortion near the zero crossing. however even with cross over distortion, high power factor and acceptable harmonics can be achieved.
NCL30002 http://onsemi.com 5 table 2. maximum ratings rating symbol value unit mfp voltage v mfp ? 0.3 to 10 v mfp current i mfp 10 ma comp voltage v control ? 0.3 to 6.5 v comp current i control ? 2 to 10 ma ct voltage v ct ? 0.3 to 6 v ct current i ct 10 ma cs voltage v cs ? 0.3 to 6 v cs current i cs 10 ma zcd voltage v zcd ? 0.3 to 10 v zcd current i zcd 10 ma drv voltage v drv ? 0.3 to v cc v drv sink current i drv(sink) 800 ma drv source current i drv(source) 500 ma supply voltage v cc ? 0.3 to 20 v supply current i cc 20 ma power dissipation (t a = 70 c, 2.0 oz cu, 55 mm 2 printed circuit copper clad) p d 450 mw thermal resistance junction ? to ? ambient (2.0 oz cu, 55 mm 2 printed circuit copper clad) junction ? to ? air, low conductivity pcb (note 3) junction ? to ? air, high conductivity pcb (note 4) r ja r ja r ja 178 168 127 c/w operating junction temperature range t j ? 40 to 125 c maximum junction temperature t j(max) 150 c storage temperature range t stg ? 65 to 150 c lead temperature (soldering, 10 s) t l 300 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: pins 1? 8: human body model 2000 v per jedec standard jesd22 ? a114e. pins 1? 8: machine model method 200 v per jedec standard jesd22 ? a115 ? a. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 3. as mounted on a 40x40x1.5 mm fr4 substrate with a single layer of 80 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 low conductivity test pcb. test conditions were under natural convection or zero air flow. 4. as mounted on a 40 x 40 x 1.5 mm fr4 substrate with a single layer of 650 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec 51 high conductivity test pcb. test conditions were under natural convection or zero air flow.
NCL30002 http://onsemi.com 6 table 3. electrical characteristics v mfp = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ? 40 c to 125 c, unless otherwise specified) characteristic test conditions symbol min typ max unit startup and supply circuits startup voltage threshold v cc increasing v cc(on) 11 12 12.5 v minimum operating voltage v cc decreasing v cc(off) 8.8 9.5 10.2 v supply voltage hysteresis h uvlo 2.2 2.5 2.8 v startup current consumption 0 v < v cc < v cc(on) ? 200 mv i cc(startup) ? 24 35 a no load switching current consumption c drv = open, 70 khz switching, v cs = 2 v i cc1 ? 1.4 1.7 ma switching current consumption 70 khz switching, v cs = 2 v i cc2 ? 2.1 2.6 ma fault condition current consumption no switching, v mfp = 0 v i cc(fault) ? 0.75 0.95 ma overvoltage and undervoltage protection overvoltage detect threshold v mfp = increasing v ovp 2.5 2.67 2.85 v overvoltage hysteresis v ovp(hys) 20 60 100 mv overvoltage detect threshold propagation delay v mfp = 1 v to 3 v step, v mfp = v ovp to v drv = 10% t ovp ? 500 800 ns undervoltage detect threshold v mfp = decreasing v uvp 0.25 0.31 0.4 v undervoltage detect threshold propagation delay v mfp = 2 v to 0 v step, v mfp = v uvp to v drv = 10% t uvp 80 200 320 ns error amplifier voltage reference t j = 25 c t j = ? 40 c to 125 c v ref 2.397 2.359 2.510 2.510 2.623 2.661 v voltage reference line regulation v cc(on) + 200 mv < v cc < 20 v v ref(line) ? 10 ? 10 mv error amplifier current capability v mfp = v ref + 0.11 v v mfp = 1.08*v ref v mfp = 0.5 v i ea(sink) i ea(sink)ovp i ea(source) 6 10 ? 11 0 10 20 ? 210 20 30 ? 250 a transconductance v mfp = v ref 100 mv t j = 25 c t j = ? 40 c to 125 c gm 90 70 110 110 120 135 s feedback pin internal pull ? down resistor v mfp = v uvp to v ref r mfp 2 4.6 10 m feedback bias current v mfp = 2.5 v i mfp 0.25 0.54 1.25 a control bias current v mfp = 0 v i control ? 1 ? 1 a maximum control voltage i control(pullup) = 10 a, v mfp = v ref v eah 5 5.5 6 v minimum control voltage to generate drive pulses v control = decreasing until v drv is low, v ct = 0 v ct (offset) 0.37 0.65 0.88 v control voltage range v eah ? ct (offset) v ea(diff) 4.5 4.9 5.3 v
NCL30002 http://onsemi.com 7 table 3. electrical characteristics (continued) v mfp = 2.4 v, v control = 4 v, ct = 1 nf, v cs = 0 v, v zcd = 0 v, c drv = 1 nf, v cc = 12 v, unless otherwise specified (for typical values, t j = 25 c. for min/max values, t j = ? 40 c to 125 c, unless otherwise specified) characteristic unit max typ min symbol test conditions ramp control ct peak voltage v comp = open v ct(max) 4.535 4.93 5.25 v on time capacitor charge current v comp = open v ct = 0 v to v ct(max) i charge 240 270 292 a ct capacitor discharge duration v comp = open v ct = v ct(max) ? 100 mv to 500 mv t ct(discharge) ? 50 150 ns pwm propagation delay dv/dt = 30 v/ s v ct = v control ? ct (offset) to v drv = 10% t pwm ? 130 220 ns zero current detection zcd arming threshold v zcd = increasing v zcd(arm) 1.25 1.4 1.55 v zcd triggering threshold v zcd = decreasing v zcd(trig) 0.6 0.7 0.83 v zcd hysteresis v zcd(hys) 500 700 900 mv zcd bias current v zcd = 5 v i zcd ? 2 ? + 2 a positive clamp voltage i zcd = 3 ma v cl(pos) 9.8 10 12 v negative clamp voltage i zcd = ? 2 ma v cl(neg) ? 0.9 ? 0.7 ? 0.5 v zcd propagation delay v zcd = 2 v to 0 v ramp, dv/dt = 20 v/ s v zcd = v zcd(trig) to v drv = 90% t zcd ? 100 170 ns minimum zcd pulse width t sync ? 70 ? ns maximum off time in absence of zcd transition falling v drv = 10% to rising v drv = 90% t start 75 165 300 s drive drive resistance i source = 100 ma i sink = 100 ma r oh r ol ? ? 12 6 20 13 rise time 10% to 90% t rise ? 35 80 ns fall time 90% to 10% t fall ? 25 70 ns drive low voltage v cc = v cc(on) ? 200 mv, i sink = 10 ma v out(start) ? ? 0.2 v current sense current sense voltage threshold t j = 25 c t j = ? 40 c to 125 c v ilim 0.475 0.470 0.485 0.485 0.495 0.500 v leading edge blanking duration v cs = 2 v, v drv = 90% to 10% t leb 100 195 350 ns overcurrent detection propagation delay dv/dt = 10 v/ s v cs = v ilim to v drv = 10% t cs 40 100 170 ns current sense bias current v cs = 2 v i cs ? 1 ? 1 a
NCL30002 http://onsemi.com 8 typical characteristics figure 3. overvoltage detect threshold vs. junction temperature figure 4. overvoltage hysteresis vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 75 50 25 0 ? 25 ? 50 2.50 2.65 2.85 100 75 25 0 ? 25 ? 50 40 50 60 70 80 v ovp , overvoltage detect threshold (v) v ovp(hys) , overvoltage hyster- esis (mv) 125 figure 5. undervoltage detect threshold vs. junction temperature figure 6. mfp pin internal pull ? down resistor vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.300 0.305 0.315 0.320 0.325 125 100 75 50 25 0 ? 25 ? 50 0 1 2 6 7 v uvp , undervoltage detect threshold (v) r mfp , feedback pin internal pull ? down resistor (m ) 0.310 figure 7. reference voltage vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.46 2.47 2.48 2.49 2.50 2.52 2.53 2.54 v ref , reference voltage (v) 50 125 3 4 5 2.51 2.55 2.70 2.60 2.75 2.80
NCL30002 http://onsemi.com 9 typical characteristics figure 8. error amplifier sink current vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 6 8 10 12 14 16 i ea(sink) , error amplifier sink current ( a) v mfp = v ref + 0.11 v t j , junction temperature ( c) f, frequency (khz) 125 100 75 50 25 0 ? 25 ? 50 85 90 95 105 110 120 125 100 10 1 0.1 0.01 200 0 20 60 100 140 160 t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 25 0 ? 25 ? 50 0.3 0.4 0.5 0.7 0.8 1.0 125 100 75 50 25 0 ? 25 ? 50 240 245 255 265 275 gm, error amplifier transconductance ( s) gm, error amplifier transconductance ( s) ct (offset) , minimum control voltage to generate drive pulses (v) i charge , ct charge current ( a) 1000 50 figure 9. error amplifier source current vs. junction temperature 180 185 190 195 200 205 215 220 ? 50 ? 25 0 25 50 75 100 125 t j , junction temperature ( c) i ea(source) , error amplifier source current ( a) figure 10. error amplifier transconductance vs. junction temperature figure 11. error amplifier transconductance and phase vs. frequency figure 12. minimum control voltage to generate drive pulses vs. junction temperature figure 13. on time capacitor charge current vs. junction temperature v mfp = 0.5 v 210 100 115 40 80 120 180 phase transconductance r control = 100 k c control = 2 pf v mfp = 2.5 vdc, 1 vac v cc = 12 v t a = 25 c 200 0 20 60 100 140 160 40 80 120 180 , phase (degrees) 0.6 0.9 250 260 270 18 20 280 290 285
NCL30002 http://onsemi.com 10 typical characteristics figure 14. ct peak voltage vs. junction temperature figure 15. pwm propagation delay vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 100 75 50 25 0 ? 25 ? 50 4.0 4.5 5.0 5.5 6.0 100 110 120 130 140 150 160 170 figure 16. current sense voltage threshold vs. junction temperature figure 17. leading edge blanking duration vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 470 473 476 479 482 485 491 494 180 190 200 210 220 figure 18. maximum off time in absence of zcd transition vs. junction temperature figure 19. drive resistance vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 165 170 175 180 190 195 200 205 125 100 75 50 25 0 ? 25 ? 50 0 2 4 8 10 14 16 18 v ct(max) , ct peak voltage (v) t pwm , pwm propagation delay (ns) v ilim , current sense voltage threshold (mv) t leb , leading edge blanking duration (ns) t start , maximum off time in ab- sence of zcd transition ( s) drive resistance ( ) 125 100 75 50 25 0 ? 25 ? 50 125 488 125 100 75 50 25 0 ? 25 ? 50 185 6 12 r oh r ol 497 500
NCL30002 http://onsemi.com 11 typical characteristics figure 20. supply voltage thresholds vs. junction temperature figure 21. startup current consumption vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 8 9 10 11 12 13 14 16 18 20 22 24 26 figure 22. switching current consumption vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 2.00 2.02 2.04 2.06 2.08 2.10 2.14 2.16 v cc , supply voltage thresholds (v) i cc(startup) , startup current consumption ( a) i cc2 , switching current con- sumption (ma) v cc(on) v cc(off) 125 100 75 50 25 0 ? 25 ? 50 2.12
NCL30002 http://onsemi.com 12 theory of operation high power factor, high ef ficiency, and small size are key parameters for led drivers in the incandescent replacement market. the NCL30002 has all the features required to accomplish that is in a compact soic-8 package. power factor is broadly defined as: pf p in (avg) v in (rms) i in (rms) this differs from the classical definition where there is a phase angle difference between the input voltage and current. however, the underlying concept of optimizing power delivery by minimizing line current is the same. ideally, current would be directly proportional to the voltage which is the case when the load is a resistor. offline power converters are active devices which are not purely resistive, capacitive, or inductive often drawing distorted current waveforms from the power lines. this distortion reduces power factor by increasing input rms current. preregulators using boost converters are the most common method to correcting the distortion and making the offline power supply appear to be a resistor as far as the power line is concerned. their performance is excellent achieving power factor greater than 0.99. regrettably, this two stage approach negatively impacts efficiency and board area. fortunately, power factors greater than 0.9 are acceptable in the general lighting market and in some applications like us energystar integral led bulbs, the minimum acceptable power factor is 0.7. so a certain amount of distortion can be accepted while maintaining high power factor. this buck topology meets the requirements for pf greater than 0.9 and regulate led current in a single power stage. unlike the boost converter, the NCL30002 buck controller operates in several different modes over the line cycle. buck modes 1. ?zero? input current (i in =0) - buck converters cannot deliver power when vin is less than vout. the ?dead time? where no current flows around the zero crossing is dependent on the line voltage and the load voltage. 2. constant on-time (t on = constant) - this is the same as the boost converter. constant t on forces the peak current to be proportional to the input voltage which is key to improved pf. 3. constant peak current (i peak = constant) ? the NCL30002 limits the peak inductor and thus the led current. in this region, the unique nature of the crm buck means that the average output current is equal to half the peak current. also the off time is fixed is this mode since the peak current and the output voltage are virtually constant. in the example below (figure 23 ) in spite of the distortion, the power factor is 0.97. the corresponding pre-filtered output current is shown in figure 24. figure 23. theoretical average input current over one half line cycle (conduction angle) mode 3 i peak = constant mode 2 t on = constant mode 1 input current = 0
NCL30002 http://onsemi.com 13 figure 24. theoretical average output current over one half line cycle (conduction angle) mode 3 i peak = constant mode 2 t on = constant mode 1 input current = 0 an output capacitor filters the output current in the led string. the dynamic led resistance, line frequency, and the size of the filter capacitance determine the exact led ripple. the NCL30002 operates as a crm controller. the controller draws very low currents while the vcc filter capacitor charges to the start-up threshold. since crm operation is not clocked at a fixed frequency and depends on the state of the power circuit to initiate a new switching cycle, a kick start timer turns on the gate driver to start a new cycle. the kick start timer will do this anytime the driver is off for more than about 180 sec as long as none of the protection circuits are disabling the gate driver output. the NCL30002 (refer to the block diagram ? figure 1) is composed of 4 key functional blocks along with protection circuitry to ensure reliable operation of the controller. ? on ? time control ? zero current detection control ? mosfet gate driver ? startup and v cc management on time control the on ? time control circuitry (figure 25) consists of a precision current source which charges up an external capacitor (c t ) in a linear ramp. the voltage on c t (after removing an internal offset) is compared to an external control voltage and the output of the comparator is used to turn off the output driver thus terminating the switching cycle. a signal from the driver is fed back to the on ? time control block to dischar ge the c t capacitor thus preparing the circuit for the start of the next switching cycle. the state of v control is determined by the external regulation loop. the range of on ? time is determined by the charging slope of the c t capacitor and is clamped at 4.93 v nominal. the c t capacitor is sized to ensure that the required on ? time is reached at maximum output power and the minimum input line voltage condition.
NCL30002 http://onsemi.com 14 figure 25. on time control comp ct + ? pwm + drv i charge t on v control ? ct (offset) t on(max) v ct v ct(off) v dd drv v control ct (offset) v eah v control off time sequence the off time is determined by the peak inductor current, the inductance and the output voltage. in mode 2, the off time is variable because the peak inductor current is not fixed. however in mode 3, the off time is constant since the peak current and the output voltage are both fixed. the auxiliary winding used to provide bias to the NCL30002 is also used to detect when the current has dropped to zero. this is illustrated in figure 26. figure 26. ideal crm waveforms with zcd winding drv v cl(neg) v zcd(trig) v zcd(arm) v cl(pos) v zcd(wind),on v zcd(wind),off v zcd(wind) v out i secondary i primary mosfet conduction output rectifier conduction t on t diode t off t sw 0 v 0 v 0 v 0 v 0 a 0 a
NCL30002 http://onsemi.com 15 zcd detection block a dedicated circuit block is necessary to implement the zero current detection . the NCL30002 provides a separate input pin to signal the controller to turn the power switch back on just after inductor current reaches zero. when the output winding current reaches zero the winding voltage will reverse. since all windings of the inductor reflect the same voltage characteristic this voltage reversal appears on the bias winding. coupling the winding voltage to the zcd input of the NCL30002 allows the controller to start the next switching cy cle at the precise t ime. to avoid false triggering, the zcd input has a dual comparator input structure to arm the latch when the zcd detect voltage rises above 1.4 v (nominal) thus setting the latch. when the voltage on zcd falls below 0.7 v (nominal) a zero current event is detected and a signal is asserted which initiates the next switching cycle. this is illustrated in figure 27. the input of the zcd has an internal circuit which clamps the positive and negative voltage excursions on this pin. the current into or out of the zcd pin must be limited to 10 ma with an external resistor. figure 27. zcd operation zcd + ? + demag + ? + reset dominant latch r q s drive zcd clamp r zcd n zcd v zcd(arm) v zcd(trig) q bias winding voltage v trig v arm at startup, there is no energy in the zcd winding and no voltage signal to activate the zcd comparators. to enable the controller to start under these conditions, an internal watchdog timer is provided which initiates a switching cycle in the event that the output drive has been off for more than 180 s (nominal). the timer is deactivated only under an ovp or uvp fault condition which will be discussed in the next section. cs the dedicated cs pin of the NCL30002 senses the current through the mosfet switch and the output inductor. if the voltage of the cs pin exceeds v ilim , the internal comparator will detect the event and turn off the mosfet. the peak switch current is calculated using equation 1: i sw(peak) v ilim r sense (eq. 1) to avoid false detection, the NCL30002 incorporates leading edge blanking circuit (leb) which masks the cs signal for a nominal time of 190 ns. if required, an optional rc filter can be added between r sense and cs to provide additional filtering. this is illustrated below. figure 28. cs circuitry with optional external rc filter cs + ? + ocp leb drv optional r sense v ilim mfp input the multi ? function pin connects to the inverting terminal of the transconductance amplifier, the undervoltage and overvoltage protection comparators. this allows this pin to perform several functions. to place the device in standby, the mfp pin should be pulled below the v uvp threshold. this is illustrated in figure 29. additionally, raising the mfp pin above v ovp will also suspend switching activity but not place the controller in the standby mode. this can be used implement overvoltage monitoring on the bias winding and add an additional layer of fault protection.
NCL30002 http://onsemi.com 16 mfp comp ea + gm uvp + ovp + ovp fault (enable ea) uvp fault c comp v control v ref bias r 1 r 2 r fb + ? + ? + ? v ovp v uvp power good shutdown figure 29. multi ? function pin operation the positive input of the transconductance amplifier is connected to a 2.51 v (nominal) reference. a filtered line feed-forward signal (see figure 2) is connected to the negative input of the error amplifier and used to control the on-time of controller. v cc management the NCL30002 incorporates a supervisory circuitry to manage the startup and shutdown of the circuit. by managing the startup and keeping the initial startup current at less than 35 a, a startup resistor connected between the rectified ac line and v cc charges the v cc capacitor to v cc(on) . turn on of the device occurs when the startup voltage has exceeded 12 v (nominal) when the internal reference and switching logic are enabled. a uvlo comparator with a hysteresis of 2.5 v nominal gives ample time for the device to start switching and allow the bias from the auxiliary winding to supply v cc. design tool the NCL30002 implements a unique control method to achieve high power and superior current regulation even though the average current is not directly sensed. there are a number of design tradeoffs that can be made between peak switch current, inductor size, and desired power factor that can impact the current regulation accuracy, efficiency, and physical size. these tradeoffs can be made by adjusting the amount of line feed forward applied, selecting the amount of time where the controller is operating in mode 2 and 3, as well as factoring in the led forward voltage range. to simplify the component selection process and allow the designer to interactively make these tradeoffs, on semiconductor has developed an excel based design guide which allows step-by-step analysis. this tool is available at onsemi.com along with a supporting application note that illustrates a complete design and provides typical application performance.
NCL30002 http://onsemi.com 17 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. NCL30002/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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